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fin224ac serdes? 22-bit bi-d irectional serializer/deserializer november 2006 ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 click here for this datasheet translated into korean! fin224ac serdes ? 22-bit bi-directional serializer/deserializer features industry smallest 22-bit serializer/ deserializer pair low power for minimum impact on battery life ? multiple power-down modes 100na in standby mode, 5ma typical operating conditions highly rolled lvcmos edge rate option to meet regulatory requirements cable reduction: 25:4 or greater differential signaling: ??90dbm emi when using ctl in lab conditions ?minimized shielding ?minimized emi filter ?minimum susceptibility to external interference up to 22 bits in either direction up to 26mhz parallel interface operation voltage translation from 1.65v to 3.6v high esd protection: > 15kv hbm parallel i/o power supply (v ddp ) range, 1.65v - 3.6v can support microcontroller or rgb pixel interface applications image sensors small displays ? lcd, cell phone, digital camera, portable gaming, printer, pda, video camera, automotive fin224ac to fin24ac comparison up to 20% power reduction double wide ckp pulse on fin224ac, mode 3 rolled edge rate for deserializer outputs on fin224ac, for single display applications same voltage range same pinout and package general description the fin224ac serdes? is a low-power serializer/ deserializer (serdes) that can help minimize the cost and power of transferring wide signal paths. through the use of serialization, the nu mber of signals transferred from one point to another can be significantly reduced. typical reduction is 4:1 to 6:1 for unidirectional paths. for bidirectional operation, using half duplex for multiple sources, it is possible to reach signal reduction close to 10:1. through the use of differential signaling, shielding and emi filters can also be minimized, further reducing the cost of serialization. the differential signaling is also important for providing a noise-insensitive signal that can withstand radio and electrical noise sources. major reduction in power consumption allows minimal impact on battery life in ultra-portable applications. a unique word boundary technique assures that the actual word boundary is identified when the data is deserialized. this guarantees that each word is correctly aligned at the deserializer on a word-by-word basis through a unique sequence of clock and data that is not repeated except at the word boundary. it is possible to use a single pll for most applications including bi-directional operation. ordering information pb-free package per jedec j-std-020b. bga and mlp packages available in tape and reel only. serdes tm is a trademark of fairchild semiconductor corporation. order number package number pb-free package description fin224acgfx bga042 yes 42-ball ultra small scale ball grid array (uss-bga), jedec mo-195, 3.5mm wide (slow lvcmos edge rate) FIN224ACMLX mlp040 yes 40-terminal molded leadless package (mlp), quad, jedec mo-220, 6mm square (slow lvcmos edge rate)
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 2 fin224ac serdes? 22-bit bi-d irectional serializer/deserializer basic concept figure 1. conceptual diagram functional block diagram figure 2. block diagram fin224ac serializer fin224ac deserializer ctl 4 lvcmos 22 lvcmos 22 ckref cks0+ cksi+ + - + - + - + - cksi- cksint cksint oe oe dso+/dsi- serializer control word ck generator freq control direction control power down control control logic 0 i word boundary generator serializer deserializer deserializer control pll register register register dso-/dsi+ diro cks0- ckp s1 s2 diri strobe dp[21:22] dp[23:24] dp[1:20] 100 termination 100 gated termination
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 3 fin224ac serdes? 22-bit bi-d irectional serializer/deserializer terminal description notes : 1. the dso/dsi serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the other device, the serial connections properly align without the need for any traces or cable signals to cross. other layout orientation may require that traces or cables cross. terminal name i/o type number of terminals description of signals dp[1:20] i/o 20 lvcmos parallel i/ o, direction controlled by diri pin dp[21:22] i 2 lvcmos parallel unidirectional inputs dp[23:24] o 2 lvcmos unidirectional parallel outputs ckref in 1 lvcmos clock input and pll reference strobe in 1 lvcmos strobe signal for latching data into the serializer ckp out 1 lvcmos word clock output dso+ / dsi- dso- / dsi+ diff-i/o 2 ctl differential serial i/o data signals (1) dso: refers to output signal pair dsi: refers to input signal pair dso(i)+: positive signal of dso(i) pair dso(i)-: negative signal of dso(i) pair cksi+ cksi- diff-in 2 ctl differential deserializer input bit clock cksi: refers to signal pair cksi+: positive signal of cksi pair cksi-: negative signal of cksi pair ckso+ ckso- diff-out 2 ctl differential serializer output bit clock ckso: refers to signal pair ckso+: positive signal of ckso pair ckso-: negative signal of ckso pair s1 in 1 lvcmos mode selection terminals used to select frequency range for the reflect, ckref s2 in 1 diri in 1 lvcmos control input used to control direction of data flow: diri = ?1? serializer diri = ?0? deserializer diro out 1 lvcmos control out put inversion of diri v ddp supply 1 power supply for parallel i/o and translation circuitry v dds supply 1 power supply for core and serial i/o v dda supply 1 power supply for analog pll circuitry gnd supply 2 for ground signals (2 for bga, 1 for mlp)
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 4 fin224ac serdes? 22-bit bi-d irectional serializer/deserializer connection diagrams figure 3. terminal assignments for bga (top view) figure 4. terminal assignments for bga (top view) 1 2 3 4 5 6 7 8 9 10 dp[9] dp[10] dp[11] dp[12] v ddp ckp dp[13] dp[14] dp[15] dp[16] 30 29 28 27 26 25 24 23 22 21 diro ckso+ ckso- dso+ dso- cksi- cksi+ diri s2 v dds 11 12 13 14 15 16 17 18 19 20 dp[17] dp[18] dp[19] dp[20] dp[21] dp[22] dp[23] dp[24] s1 v dda 40 39 38 37 36 35 34 33 32 31 dp[8] dp[7] dp[6] dp[5] dp[4] dp[3] dp[2] dp[1] strobe ckref pin assignments 1234 5 6 a dp[9] dp[7] dp[5] dp[3] dp[1] ckref b dp[11] dp[10] dp[6] dp[2] strobe diro c ckp dp[12] dp[8] dp[4] ckso+ ckso- d dp[13] dp[14] vddp gnd d so-/dsi+ dso+/dsi- e dp[15] dp[16] gnd vdds cksi+ cksi- f dp[17] dp[18] dp[21] vdda s2 diri j dp[19] dp[20] dp[ 22] dp[23] dp[24] s1
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 5 control logic circuitry the fin224ac has the ability to be used as a 22-bit seri- alizer or a 22-bit deserializer. pins s1 and s2 must be set to accommodate the clock reference input frequency range of the serializer. table 1 shows the pin program- ming of these options based on the s1 and s2 control pins. the diri pin controls whether the device is a serial- izer or a deserializer. when diri is asserted low, the device is configured as a deserializer. when the diri pin is asserted high, the device is configured as a serial- izer. changing the state on the diri signal reverses the direction of the i/o signals and generate the opposite state signal on diro . for unidirectional operation the diri pin should be hardwired to the high or low state and the diro pin should be left floating. for bi-direc- tional operation, the diri of the master device is driven by the system and the diro signal of the master is used to drive the diri of the slave device. serializer/deserializer with dedicated i/o variation the serialization and deserialization circuitry is set up for 24 bits. because of the dedicated inputs and outputs, only 22 bits of data are ever serialized or deserialized. regardless of the mode of operation, the serializer is always sending 24 bits of data plus 2 boundary bits and the deserializer is always receiving 24 bits of data and 2 word boundary bits. bits 23 and 24 of the serializer always contain the value of zero and are discarded by the deserializer. dp[21:22] input to the serializer is dese- rialized to dp[23:24] respectively. turn-around functionality the device passes and invert s the diri signal through the device asynchronously to the diro signal. care must be taken by the system designer to ensure that no contention occurs between the deserializer outputs and the other devices on this port. optimally the peripheral device driving the serializer should be put into a high- impedance state prior to the diri signal being asserted. when a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. this value only changes if the device is once again turned around into a deserializer and the va lues are overwritten. power-down mode: (mode 0) mode 0 is used for powering down and resetting the device. when both of the mode signals are driven to a low state, the pll and refere nces are disabled, differ- ential input buffers are shut off, differential output buffers are placed into a high-imp edance state, lvcmos out- puts are placed into a high-impedance state, and lvc- mos inputs are driven to a valid level internally. additionally all internal circuitry is reset. the loss of ckref state is also enabled to ensure that the pll only powers-up if there is a valid ckref signal. in a typical application mode, signals of the device do not change states other than be tween the desired frequency range and the power-down mode. this allows for sys- tem-level power-down functionality to be implemented via a single wire for a serdes pair. the s1 and s2 selec- tion signals that have their operating mode driven to a ?logic 0? should be hardwired to gnd. the s1 and s2 signals that have their operating mode driven to a ?logic 1? should be connected to a system-level power-down or reset signal. table 1. control logic circuitry mode number s2 s1 diri description 0 0 0 x power-down mode 1 0 1 1 22-bit serializer 2mhz to 5mhz ckref 0 1 0 22-bit deserializer 2 1 0 1 22-bit serializer 5mhz to 15mhz ckref 1 0 0 22-bit deserializer 3 1 1 1 22-bit serializer 10mhz to 26mhz ckref (divide by 2 serial data) (note: fin224c required for rgb applications) 1 1 0 22-bit deserializer
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 6 serializer operation mode the serializer configurations are described in the following sections. the basic serializat ion circuitry works essentially identically in these modes, but the actual data and clock st reams differ depending on if ckref is the same as the strobe signal or not. when it is stated that ckref doe s not equal strobe, each signal is distinct and ckref must be running at a frequency high enough to avoid any lo ss of data condition. ckref must never be a lower fre- quency than strobe. the pll must receive a stable ckref signal to achieve lock prior to any valid data being sent. the ckref signal can be used as the data strobe signal provided that data can be ignored during the pll lock phase. once the pll is stable and locked, the device can begin to capture and serialize data. data is captured on the rising edge of the strobe signal and then serial- ized. the serialized data stream is syn chronized and sent source synchronously with a bit clock with an embedded word boundary. when operating in this mode, the internal deserializer circuitry is disabl ed, including the serial clock, serial data input buffers, the bi-directional parallel outputs, and the ckp word clock. the ckp word clock is driven high. figure 5. serializer timing diagram (ckref = strobe) if the same signal is not used for ckref and strobe, the ckref signal must be run at a higher frequency than the strobe rate to serialize the data cor- rectly. the actual serial transfer rate remains at 13 times the ckref frequency. a data bit value of zero is sent when no valid data is present in the serial bit stream. the operation of the serializer otherwise remains the same. the exact frequency that the reference clock needs to run at depends upon the stability of the ckref and strobe signal . if the source of the ckref signal implements spread spectrum technology, th e max frequency of the spread spec- trum clock should be used in calculating the ratio of strobe frequency to the ckref frequency. similarly, if the st robe signal has signifi cant cycle-to-cycle variation, the maximum cycle- to-cycle time needs to be factored into the selec- tion of the ckref frequency. figure 6. serializer timing diagram (ckref does not equal strobe) word n-1 word n-2 word n-1 word n dpi[1:24] ckref/strobe dso cks0 b 24 b 25 b 26 b 1 b 2 b 3 b 4 b 1 b 2 b 3 b 4 b 5 b 22 b 23 b 24 b 25 b 26 word n+1 word n word n-1 word n-1 word n no data no data ckref dp[1:24] dso cks0 strobe b 1 b 2 b 3 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 22 b 23 b 24 b 25 b 26 word n+1 word n serializer operation: (figure 5) mode 1 or mode 2, diri = 1, ckref = strobe serializer operation: (figure 6), diri = 1, ckref does not = strobe
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 7 serializer operation mode (continued) when operating in mode 3, t he effective serial speed is divided by two. this mode has been implemented to accommo date cases where the reference clock frequency is high compared to the actual strobe frequency. the actual strobe frequency must be less than or equal to 50% of the ckref frequency for this mode to work properly. this mode, in all other ways, operates the same as described in the section where ckref does not equal strobe. figure 7. ckref > 2x strobe frequency; mode 3 operation (s1 = s2 = 1) a third method of serialization can be acheived by providing a free-running bit clock on the cksi signal. this mode is enabled by grounding the ckref signal and driving the diri signal high. at power-up, the device is configured to accept a serialization clock from cksi. if a ckref is received, this device enables the ckref serialization mode. the device remains in this mode even if ckref is stopped. to re-enable this mode, the device must be powered down and then powered back up with a ?logic 0? on ckref. figure 8. serializer timing diagra m using provided bit clock (no ckref) no data word n-1 word n dp[1:24] word n-1 word n word n+1 no data ckref dso b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 22 b 23 b 24 b 25 b 26 b 1 b 2 b 3 cks0 strobe word n-1 word n-1 word n no data no data dp[1:24] dso cks0 cksi strobe b 1 b 2 b 3 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 22 b 23 b 24 b 25 b 26 word n+1 word n serializer operation: (figure 7), mode 3 (s1 = s2 = 1), diri = 1, ckref divide by 2 mode serializer operation: (figure 8), diri = 1, no ckref
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 8 deserializer op eration mode the operation of the deserializer is onl y dependent upon the data received on the dsi data signal pair and the cksi clock signal pair. the following two sections describe the operation of the deserializer under two distinct serializer source conditions. references to the ckref and strobe signals refer to the signals associated with the serializer device used in generating the serial data and clock signals that are inputs to the deserializer. when operating in this mode, the internal serializer circuitry is disabled, including the parallel data input buffers. if there is a ckref signal provided, the ckso serial clock continues to transmit bit clocks. upon device power-up (s1 or s2 = 1), all deserializer output data pins are driven low until vali d data is passed through the deserializer. when the diri signal is asserted low, the device is configured as a deserial- izer. data is captured on the serial port and deserialized through use of the bit clock sent with the data. the word boundary is defined in the actual clock and data signal. parallel data is generated at the time the word boundary is defined in the actual clock and data signal. parallel data is generated at the time the word boundary is detected. the falling edge of ckp occurs approximately six bit times after the falling edge of cksi. the rising edge of ckp goes high approxi- mately 13 bit times after ckp goes low. the rising edge of ckp is generated approximately 13 bit times later. when no embedded word boundary occurs, no pulse on ckp is generated and ckp remains high. figure 9. deserializer timing diagram (serializer source: ckref equals strobe) the logical operation of the deserializer remains the same if the ckref is equal in frequency to the strobe or at a higher frequency than the strobe. the actual serial data stream presented to th e deserializer is different because it has non-valid data bits sent between words. the duty cycle of ckp varies based on the ratio of the frequency of the ckref signal to the strobe signal. the fre- quency of the ckp signal is equal to the strobe frequency. the falling edge of ckp occurs six bit times after the data transition. the low time of the ckp sig- nal is equal to 13 serial bit times. in modes 1 and 2, the ckp low time equals half of the ckref period of the serializ er. in mode 3, the ckp low is equal to the ckref period. the ckp high time is approximately equal to the strobe period, minus the ckp low time. figure 10 is representative of a waveform that could be seen when ckref is not equal to strobe. if ckref was significantly faster, additional non-valid data bits would occur between data words. figure 10. deserializer timi ng diagram (serializer source : ckref does not equal strobe) word n-1 word n+1 word n b 24 b j b j+1 b j+13 b j+14 b 25 b 26 b 24 6 bit times 13 bit times b 25 b 26 00 00 word n-2 dp[1:24] ckpo cksi dsi word n word n-1 word n-1 word n+1 word n b 24 b 25 b 26 b 1 b 1 b 2 b 6 b 7 b 8 b 9 b 24 b 19 b 20 b 25 b 26 word n-2 dp[1:24] ckpo cksi dsi word n word n-1 deserializer operation: diri = 0 (serializer source: ckref = strobe) deserializer operation: diri = 0 (serializer source: ckref does not = strobe)
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 9 lvcmos data i/o the lvcmos input buffers have a nominal threshold value equal to half v dd . the input buffers are only oper- ational when the device is operating as a serializer. when the device is operating as a deserializer, the inputs are gated off to conserve power. the lvcmos 3-state output buffers are rated for a source / sink current of ap proximately 0.5ma at 1.8v. the outputs are active when the diri signal and either s1 or s2 is asserted high. when the diri signal and either s1 or s2 is asserted low, the bi-directional lvc- mos i/os is in a high-z state. under purely capacitive load conditions, the outpu t swings between gnd and v ddp . when s1 or s2 initially transitions high, the initial state of the deserializer lvcmos outputs is zero. unused lvcmos input buffers must be either tied off to a valid logic low or a valid logic high level to prevent static current draw due to a floating input. unused lvc- mos output should be left floating. unused bi-directional pins should be connected to gnd through a high-value resistor. if a fin224ac devi ce is configured as an unidi- rectional serializer, unused data i/o can be treated as unused inputs. if the fin224ac is hardwired as a deseri- alizer, unused data i/o can be treated as unused outputs. the fin224ac family offers fast and slow lvcmos edge rates to meet emissions and loading requirements. differential i/o circuitry the fin224ac employs fsc proprietary current tran- sistor logic (ctl) input / ou tput (i/o) technology. ctl is a low-power, low-emi differential swing i/o technology. the ctl output driver ge nerates a constant output source and sink current. the ctl input receiver senses the current difference and direction from the correspond- ing output buffer to which it is connected. this differs from lvds, which uses a constant current source output, but a voltage sense receiver. like lvds, an input source termination resistor is requir ed to properly terminate the transmission line. the fin224ac device incorporates an internal termination resistor on the cksi receiver and a gated internal termination resistor on the ds input receiver. the gated termination resistor ensures proper termination regardless of direction of data flow. the rela- tive greater sensitivity of the current sense receiver of ctl allows it to work at much lower current drive and a much lower voltage. during power down mode, the differential inputs are dis- abled and powered down and the differential outputs are placed in a high-z state. ctl inputs have an inherent failsafe capability that suppor ts floating inputs. when the cksi input pair of the serializ er is unused, it can reliably be left floating. alternately both of the inputs can be con- nected to ground. ctl inputs should never be connected to vdd. when the ckso output of the deserializer is unused, it should be allowed to float. figure 11. bi-directional differential i/o circuitry phase-locked loop (pll) circuitry the ckref input signal is used to provide a reference to the pll. the pll generates internal timing signals capa- ble of transferring data at 13 times the incoming ckref signal. the output of the pll is a bit clock that is used to serialize the data. the bit clock is also sent source syn- chronously with the serial data stream. there are two ways to disable the pll. the pll can be disabled by entering the mode 0 state (s1 = s2 = 0). the pll dis- ables immediately upon detecting a low on both the s1 and s2 signals. when any of the other modes are entered by asserting either s1 or s2 high and by pro- viding a ckref signal, the pll powers-up and goes through a lock sequence. one must wait the specified number of clock cycles prior to capturing valid data into the parallel port. + + ds+ ds- gated termination (ds pins only) from serializer to deserializer from control
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 10 application mode diagrams figure 12. fin224ac rgb figure 13. fin224ac microcontroller flex circuit design guidelines the serial i/o information is transmitted at a high serial rate. care must be taken implementing this serial i/o flex cable. the following best practices should be used when developing the flex cabling or flex pcb: keep all four differential wires the same length. allow no noisy signals over or near differential serial wir es. example: no lvcmos traces over differential wires. use only one ground plane or wire over the differential serial wires. do not run ground over top and bottom. do not place test points on differential serial wires. use differential serial wires a mini mum of 2cm away from the antenna. u20 2.8v 1.8v vddp 2.8v 2.8v lcd14_m lcd10_m lcd2_m lcd6_m lcd8_m lcd12_m lcd4_m lcd1_m lcd15_m lcd5_m lcd11_m lcd9_m lcd7_m lcd13_m pixclk_m lcd3_m gpio_mode lcd_enable_m lcd16_m lcd17_m lcd0_s lcd0_m lcd_hsync_m lcd_vsync_m lcd1_s lcd2_s lcd3_s lcd4_s lcd5_s lcd6_s lcd7_s lcd8_s lcd9_s lcd10_s lcd11_s lcd12_s lcd13_s lcd14_s lcd15_s lcd16_s lcd17_s lcd_hsync_s lcd_vsync_s pixclk_s serdes serializer lcd controller out lcd display in assumptions: 1) 18-bit unidirectional rgb application 2) mode 2 operation (5mhz to 15mhz ckref) serdes deserializer 3) vddp= (1.65v to 3.6v) fin224ac u22 dp9 a1 dp7 a2 dp5 a3 dp3 a4 dp1 a5 ckref a6 dp11 b1 dp10 b2 dp6 b3 dp2 b4 strobe b5 diro b6 ckp c1 dp12 c2 dp8 c3 dp4 c4 ckso+ c5 ckso- c6 dp13 d1 dp14 d2 vddp d3 gnd d4 dso-/dsi+ d5 dso+/dsi- d6 cksi- e6 cksi+ e5 vdds e4 gnd e3 dp16 e2 dp15 e1 diri f6 s1 f5 vdda f4 dp21 f3 dp18 f2 dp17 f1 s2 j6 dp24 j5 dp23 j4 dp22 j3 dp20 j2 dp19 j1 tp6 1nf c10 1nf 1nf c6 1nf .01f c12 fin224ac dp9 a1 dp7 a2 dp5 a3 dp3 a4 dp1 a5 ckref a6 dp11 b1 dp10 b2 dp6 b3 dp2 b4 strobe b5 diro b6 ckp c1 dp12 c2 dp8 c3 dp4 c4 ckso+ c5 ckso- c6 dp13 d1 dp14 d2 vddp d3 gnd d4 dso-/dsi+ d5 dso+/dsi- d6 cksi- e6 cksi+ e5 vdds e4 gnd e3 dp16 e2 dp15 e1 diri f6 s2 f5 vdda f4 dp21 f3 dp18 f2 dp17 f1 s1 j6 dp24 j5 dp23 j4 dp22 j3 dp20 j2 dp19 j1 tp5 .01f c3 c11 2.2f lcd_enable_s 2.8v 1.8v vddp 2.8v 2.8v lcd14_m lcd10_m lcd2_m lcd6_m lcd8_m lcd12_m lcd4_m lcd1_m lcd15_m lcd5_m lcd11_m lcd9_m lcd7_m lcd13_m refclk lcd3_m gpio_mode lcd_/write_enable_m lcd16_m lcd17_m lcd0_s lcd0_m lcd_address_m lcd_/cs_m lcd1_s lcd2_s lcd3_s lcd4_s lcd5_s lcd6_s lcd7_s lcd8_s lcd9_s lcd10_s lcd11_s lcd12_s lcd13_s lcd14_s lcd15_s lcd16_s lcd17_s lcd_address_s lcd_/cs_s lcd_/write_enable_s serdes serializer lcd controller out lcd display in assumptions: 1) 18-bit unidirectional ?ontroller application 2) mode 3 operation (10 mhz to 20mhz ckref) serdes deserializer 3) vddp= (1.65v to 3.6v) 4) refclk is a continously running clock with a frequency greater than /write_enable. u23 fin224ac u23 fin224ac dp9 a1 dp7 a2 dp5 a3 dp3 a4 dp1 a5 ckref a6 dp11 b1 dp10 b2 dp6 b3 dp2 b4 strobe b5 diro b6 ckp c1 dp12 c2 dp8 c3 dp4 c4 ckso+ c5 ckso- c6 dp13 d1 dp14 d2 vddp d3 gnd d4 dso-/dsi+ d5 dso+/dsi- d6 cksi- e6 cksi+ e5 vdds e4 gnd e3 dp16 e2 dp15 e1 diri f6 s2 f5 vdda f4 dp21 f3 dp18 f2 dp17 f1 s1 j6 dp24 j5 dp23 j4 dp22 j3 dp20 j2 dp19 j1 tp2 tp2 1nf c7 1nf c7 1nf c5 1nf c5 .01uf c9 .01? c9 tp1 tp1 u21 fin224ac u21 fin224ac dp9 a1 dp7 a2 dp5 a3 dp3 a4 dp1 a5 ckref a6 dp11 b1 dp10 b2 dp6 b3 dp2 b4 strobe b5 diro b6 ckp c1 dp12 c2 dp8 c3 dp4 c4 ckso+ c5 ckso- c6 dp13 d1 dp14 d2 vddp d3 gnd d4 dso-/dsi+ d5 dso+/dsi- d6 cksi- e6 cksi+ e5 vdds e4 gnd e3 dp16 e2 dp15 e1 diri f6 s2 f5 vdda f4 dp21 f3 dp18 f2 dp17 f1 s1 j6 dp24 j5 dp23 j4 dp22 j3 dp20 j2 dp19 j1 tp3 tp3 .01uf c2 .01? c2 c8 2.2uf c8 2.2?
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 11 absolute maximum ratings the ?absolute maximum ratings? are those values beyon d which the safety of t he device cannot be guaranteed. the device should not be operated at these limits. the pa rametric values defined in the electrical characteristics tables are not guaranteed at the abs olute maximum ratings. the ?recommended operating conditions? table defines the conditions for actual device operation. recommended operat ing conditions notes : 2. absolute maximum ratings are dc values beyond which the de vice may be damaged or have its useful life impaired. the datasheet specification shou ld be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. fairch ild does not recommend operation outside datasheet specifications. symbol parameter min. max. unit v dd supply voltage -0.5 +4.6 v all input/output voltage -0.5 +4.6 v ctl output short circuit duration continuous t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature +260 c esd human body model, 1.5k , 100pf all pins >2 kv s1, s2, ckso, cksi, dso, dsi, vdda, vdds, vddp (as specified in iec61000-4-2) >15 kv symbol parameter min. max. unit v dda , v dds supply voltage 2.5 3.3 v v ddp supply voltage 1.65 3.60 v t a operating temperature (2) -30 +70 c v dda-pp supply noise voltage 100 mvp-p
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 12 dc electrical characteristics over-supply voltage and operating temperat ure ranges, unless otherwise specified. notes : 3. typical values are given for v dd = 2.775v and t a = 25c. positive current values re fer to the current flowing into the device and negative values refer to the current flowing out of the pins. voltages are referenced to ground unless otherwise specified (except v od and v od ). symbol parameter test conditions min. typ. (3) max. unit lvcmos i/o v ih input high voltage 0.65 x v ddp v ddp v il input low voltage gnd 0.35 x v ddp v v oh output high voltage i oh = 2.0ma v ddp = 3.30.30 0.75 x v ddp v v ddp = 2.5-0.20 v ddp = 1.80.18 v ol output low voltage i ol = 2.0ma v ddp = 3.30.30 0.25 x v ddp v v ddp = 2.50.20 v ddp = 1.80.18 i in input current v in = 0v to 3.6v -5.0 5.0 a differential i/o i odh output high source current v os = 1.0v -1.75 a i odl output low sink current v os = 1.0v 0.950 a i os short-circuit output current v out = 0v driver enabled ma driver disabled 5 a i oz disabled output leakage current ckso, dso = 0v to v dds s2 = s1 = 0v 1 5 a i th differential input threshold high current see figure 6 and table 2 50 a i tl differential input threshold low current see figure 6 and table 2 -50 a i iz disabled input leakage current cksi, dsi = 0v to v dds s2 = s1 = 0v 1 5 ua i is short-circuit input current vout =v dds ma v icm input common mode range v dds = 2.775 5% 0.5 v dds-1 v r trm cksi, ds internal receiver termination resistor v id = 50mv, v ic = 925mv, diri = 0 | cksi + ? cksi ? | = v id 100
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 13 power supply currents notes : 4. typical values are given for v dd = 2.775v and t a = 25c. positive current values re fer to the current flowing into the device and negative values refer to the current flowing out of the pins. voltages are referenced to ground unless otherwise specified (except v od and v od ). symbol parameter test conditions min. typ. (4) max. unit idda1 vdda serializer static supply cur- rent all dp and control inputs at 0v or nockref, s2 = 0, s1 = 1, dir = 1 450 a idda2 vdda deserializer static supply current all dp and control inputs at 0v or nockref, s2 = 0, s1 = 1, dir = 0 550 a idds1 vdds serializer static supply cur- rent all dp and control inputs at 0v or nockref, s2 = 0, s1 = 1, dir = 1 4 ma idds2 vdds deserializer static supply current all dp and control inputs at 0v or nockref, s2 = 0, s1 = 1, dir = 0 4.5 ma idd_pd vdd power-down supply current idd_pd = idda s1 = s2 = 0 all inputs at gnd or vdd 0.1 a idd_ser1 26:1 dynamic serializer power supply current idd_ser1 = idda+idds+iddp ckref = strobe diri = h s2 = 0 s1 = 1 2mhz 9 ma 5mhz 14 s2 = 1 s1 = 0 5mhz 9 15mhz 17 s2 = 1 s1 = 1 10mhz 9 26mhz 16 idd_des1 26:1 dynamic deserializer power supply current idd_des1 = idda+idds+iddp ckref = strobe diri = l s2 = 0 s1 = 1 2mhz 5 ma 5mhz 6 s2 = 1 s1 = 0 5mhz 4 15mhz 5 s2 = 1 s1 = 1 10mhz 7 26mhz 11 idd_ser2 26:1 dynamic serializer power supply current idd_ses2 = idda+idds+iddp no ckref strobe active cksi = 15x strobe diri = h 2mhz 8 ma 5mhz 8 10mhz 10 15mhz 12
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 14 fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ac electrical characteristics characteristics at recommended over-supply voltage and o perating temperature ranges, unless otherwise specified. symbol parameter test conditions min. typ. (5) max. unit serializer input operating conditions t tcp ckref clock period (2mhz ? 26mhz) ckref = strobe see figure 14 s2=0 s1=1 s2=1 s1=0 s2=1 s1=1 200 66 38.46 t 500 200 100.00 ns f ref ckref frequency relative to strobe ckref does not = strobe s2=0 s1=1 2.25 x f strobe mhz t cpwh ckref clock high time 0.2 0.5 t t cpwl ckref clock low time 0.2 0.5 t t clkt lvcmos input transition time see figure 16 90.0 ns t spwh strobe pulse width high/low see figure 16 (tx4)/26 (tx22)/26 ns f max maximum serial data rate ckref x 26 s2=0 s1=1 s2=1 s1=0 s2=1 s1=1 52 130 260 130 390 676 mb/s t stc dp (n) setup to strobe diri = 1 2.5 ns t htc dp (n) hold to strobe 2.0 ns serializer ac electrical characteristics t tccd transmitter clock input to clock output delay ckref = strobe 33a+1.5 35a+6.5 ns t spos ckso position relative to ds (6) -50.0 250.0 ps pll ac electrical characteristics t tplls0 serializer phase lock loop stabilization time see figure 18 200 s t tplld0 pll disable time loss of clock see figure 21 30.0 s t tplld1 pll power-down time (7) see figure 22 20.0 ns deserializer input operating conditions t s_ds serial port setup time, ds-to-cksi (8) 1.4 ns t h_ds serial port hold time, ds-to-cks (8) -250 ps deserializer ac electrical characteristics t rcop deserializer clock output (ckp out) period (9) see figure 17 50.0 t 500.0 ns t rcol ckp out low time see figure 17 (rising edge strobe) (9) serial- izer source strobe = ckref 13a-3 13a+3 ns t rcoh ckp out high time 13a-3 13a+3 ns t pdv data valid to ckp low see figure 17 (rising edge strobe) 8a-6 8a+1 ns t rolh (fin224ac) output rise time (20% to 80%) c l = 8pf see figure 14 18 ns t rohl (fin224ac) output fall time (20% to 80%) c l = 8pf see figure 14 18 ns
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 15 fin224ac serdes? 22-bit bi-d irectional serializer/deserializer notes : 5. typical values are given for v dd = 2.775v and t a = 25c. positive current values refer to the current flowing into device and negative values means current flowing out of the pins. voltages are referenced to ground unless otherwise specified (except dvod and vod). 6. skew is measured from either the ri sing or falling edge of ckso clock to the rising or falling edge of data (dso). signals are edge aligned. both outputs should have iden tical load conditions for this test to be valid. 7. the power-down time is a function of the ckref frequency prior to ckref being stopped high or low and the state of the s1/s2 mode pins . the specific number of clock cycles requ ired for the pll to be disabled varies dependent upon the operatin g mode of the device. 8. signals are transmitted from the serializer source synchron ously. note that, in some cases, data is transmitted when the clock remains at a high state. skew should only be measured when data and clock are transitioning at the same time. total measured input skew would be a combination of ou tput skew from the serializer, load variations, and isi and jitter effects. 9. (a = (1/f)/13) rising edge of ckp appears approximately 13 bit time s after the falling edge of the ckp output. falling edge of ckp occurs approximately eight bit times after a dat a transition or six bit times after the falling edge of ckso. variation of the data with respect to the ckp signal is due to internal propagation delay differences of the data and ckp path and propagation delay differences on the va rious data pins. note that if the ckref is not equal to strobe for the serializer, the ckp signal does not mainta in a 50% duty cycle.the low time of ckp remains 13 bit times. control logic timing controls notes : 10. deserializer enable time includes the time required for inte rnal voltage and current referenc es to stabilize. this time is significantly less than the pll lock time and th erefore does not limit over all system startup time. capacitance symbol parameter test conditi ons min. typ. max. units t phl_dir , t plh_dir propagation delay diri-to-diro diri low-to-high or high-to-low 17.0 ns t plz , t phz propagation delay diri-to-dp diri low-to-high 25.0 ns t pzl , t pzh propagation delay diri-to-dp diri high-to-low 25.0 ns t plz , t phz deserializer disable time: s0 or s1 to dp diri = 0, s1(2) = 0 and s2(1) = low-to-high figure 23 25.0 ns t pzl , t pzh deserializer enable time: s0 or s1 to dp diri = 0, (10) s1(2) = 0 and s2(1) = low-to-high figure 23 2.0 s t plz , t phz serializer disable time: s0 or s1 to ckso, ds diri = 1, s1(2) = 0 and s2(1) = high-to-low figure 22 25.0 ns t pzl , t pzh serializer enable time: s0 or s1 to ckso, ds diri = 1, s1(2) and s2(1) = low-to-high figure 22 65.0 ns symbol parameter test conditions min. typ. max. units c in capacitance of input only signals, ckref, strobe, s1, s2, diri diri = 1, s1 = s2 = 0, v dd = 2.5v 2.0 pf c io capacitance of parallel port pins dp 1:12 diri = 1, s1 = s2 = 0, v dd = 2.5v 2.0 pf c io-diff capacitance of differential i/o sig- nals diri = 0, s1 = s2 = 0, v dd = 2.775v 2.0 pf
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 16 fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ac loading and waveforms figure 14. lvcmos output load figure 15. serial setup and hold time and transition times figure 16. lvcmos clock parameters figu re 17. deserializer data valid window time and clock output parameters figure 18. serializer pll lock time figure 19. serializer clock propagation delay t rolh 20% dpn dpn 20% 80% 80% 8pf t rohl setup: strobe dp[1:12] strobe t stc t htc data data dp[1:12] setup time hold time mode0 = 0?or ?, mode1 = 1? ser/des = 1 ckref t clkt 90% 90% 10% 10% 50% 50% t clkt v ih v il t tcp t cpwh t cpwl ckp dp[1:12] t pdv data data time en_des = ?? cksi and dsi are valid signals ckref 50% 75% 50% 25% t rcop t rcoh t rcol setup: cks0 ckref s1 or s2 v dd /v dda t tpls0 note: ckref signal is free running. strobe cks0- cks0+ t tccd v dd/2 v diff = 0 note: strobe = ckref
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 17 fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ac loading and waveforms (continued) figure 20. deserializer clock propagation de lay figure 21. pll loss of clock disable time figure 22. pll power-down time figure 23. serializer enable and disable time figure 24. deserializer enable and disable times cksi- cksi+ ckp t rccd v dd/2 v diff = 0 cks0 ckref t tppld0 note: ckref signal can be stopped either high or low cks0 s1 or s2 t tppld1 ds+,cks0+ highz ds+,cks0- s1 or s2 t plz(hz) t pzl(zh) note: ckref must be active and pll must be stable s1 or s2 dp t plz(hz) t pzl(zh) note: if s1(2) transitioning then s2(1) must = 0 for test to be valid
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 18 tape and reel specification bga embossed tape dimension dimensions are in millimeters. notes : a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c) . shipping reel dimensions package a 0 b 0 d d 1 e f k 0 p 1 p 0 p 2 t t c w w c 3.5 x 4.5 tbd 0.1 tbd 0.1 1.55 0.05 1.5 min. 1.75 0.1 5.5 0.1 1.1 0.1 8.0 typ. 4.0 typ. 2.0 0/05 0.3 typ. 0.07 0.005 12.0 0.3 9.3 typ. p 1 a 0 d 1 p 0 p 2 f w e d b 0 tc w c k 0 t user direction of feed
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 19 dimensions are in millimeters. tape width dia a dim b dia c dia d dim n dim w1 dim w2 dim w3 (lsl?usl) 8 330 max. 1.5 min. 13.0 +0.5/?0.2 20.2 min. 178 min. 8.4 +2.0/?0 14.4 max. 7.9 ~ 10.4 12 18.4 max. 11.9 ~ 15.4 16 22.4 max. 15.9 ~ 19.4 10? maximum component rotation sketch c (top view) component lateral movement typical component cavity center line 1.0mm maximum w1 measured at hub dia a max dia d min b min dia c dia n see detail aa detail aa w3 w2 max measured at hub 1.0mm maximum typical component center line 10 maximum b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 20 tape and reel specification (continued) mlp embossed tape dimension dimensions are in millimeters. notes : ao, bo, and ko dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c ). shipping reel dimension dimensions are in millimeters. package a 0 b 0 d d 1 e f k 0 p 1 p 0 p 2 t t c w w c 5 x 5 5.35 0.1 5.35 0.1 1.55 0.05 1.5 min. 1.75 0.1 5.5 0.1 1.4 0.1 8 typ. 4 typ. 2.0 0.05 0.3 typ. 0.07 0.005 12 0.3 9.3 typ. 6 x 6 6.30 0.1 6.30 0.1 tape width dia a dim b dia c dia d dim n dim w1 dim w2 dim w3 (lsl?usl) 8 330 max. 1.5 min. 13.0 +0.5/?0.2 20.2 min. 178 min. 8.4 +2.0/?0 14.4 max. 7.9 ~ 10.4 12 18.4 max. 11.9 ~ 15.4 16 22.4 max. 15.9 ~ 19.4 p 1 a 0 d 1 p 0 p 2 f w e d b 0 tc w c k 0 t user direction of feed 10? maximum component rotation sketch c (top view) component lateral movement typical component cavity center line 1.0mm maximum w1 measured at hub dia a max dia d min b min dia c dia n see detail aa detail aa w3 w2 max measured at hub 1.0mm maximum typical component center line 10 maximum b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 21 physical dimensions dimensions are in millimet ers unless otherwise noted. figure 25. pb-free 42-ball ultra small scale ball grid array (uss-bga), jedec mo-195, 3.5mm wide bottom view 3.50 4.50 0.5 0.5 3.0 2.5 ?0.30.05 seating plane 0.230.05 0.450.05 (0.75) (0.5) (0.35) (0.6) 0.08 c 0.10 c 0.10 c 0.890.082 1.00 max 0.210.04 (qa control value) 0.10 c c 0.15 c a b 0.05 c x42 terminal a1 corner index area 2x 2x 0.2 +0.1 -0.0 land pattern recommendation
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 22 physical dimensions (continued) dimensions are in millimet ers unless otherwise noted. figure 26. pb-free 40-terminal molded leadless package (mlp), quad, jedec mo-220, 6mm square (datum a)
fin224ac serdes? 22-bit bi-d irectional serializer/deserializer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.2 23

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